The present invention relates to a bump formation technology in a manufacturing method of a semiconductor integrated circuit device (or a semiconductor device), in particular it relates to a technology that is effective for application to a gold (Au) bump formation technology.
In Japanese Patent Laid-Open No. 2006-291242 (Patent Document 1), with regard to formation of Au bumps over a semiconductor chip to be supplied for an assembling process, such as TCP (Tape Carrier Package), COF (Chip On Film or Chip On Flex), or COG (Chip On Glass), a technology, in which, in order to form an Au plated layer having relatively larger grains, the temperature and the thallium (Tl) concentration of a gold sulfite based (non-cyan based) plating solution are set to be relatively higher, has been disclosed.
In Japanese Patent Laid-Open No. 2006-322037 (Patent Document 2), with regard to formation of Au bumps over a semiconductor chip, a technology, in which, in order to form Au bumps having relatively lower hardness and good looking shapes, the temperature and the Tl concentration of the gold sulfite based (non-cyan based) plating solution are set to be relatively higher, has been disclosed.
In Japanese Patent Laid-Open No. 2009-114476 (Patent Document 3) or US Patent Application Publication No. US 2009/0117730 (Patent Document 4), with regard to formation of Au bumps over a semiconductor chip, a technology for preventing protrusions due to deposits in a plating cup from being generated over bump electrodes has been disclosed.